Via in semiconductor device structure

ABSTRACT

A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer. The semiconductor device structure includes an insulating capping layer formed over the gate electrode layer, and the insulating capping layer covers a top surface of the gate dielectric layer. The semiconductor device structure also includes a conductive via structure formed through the insulating capping layer, and a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application is a Continuation application of U.S. Pat. Application Ser. No. 17/018,356, filed on Sep. 11, 2020, which is a Divisional of pending U.S. Pat. Application Ser. No. 16/260,536, filed Jan. 29, 2019, the entirety of which are incorporated by reference herein.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET).

Although advantages of the FinFET may include reducing the short channel effect and raising the current flow, fabrication processes continue to become more difficult to perform since feature sizes continue to decrease. For example, there is a challenge to form reliable via structures for the FinFET at smaller and smaller sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A to 1D illustrate perspective views of various stages of manufacturing a semiconductor device structure in accordance with some embodiments.

FIGS. 2A to 2Q illustrate cross-sectional representations of various stages of manufacturing the semiconductor device structure in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Embodiments for manufacturing semiconductor device structures are provided. The semiconductor device structures may include a gate structure and an adjacent source/drain contact structure over a fin structure of the semiconductor substrate. The gate structure is covered with an insulating capping layer. An insulating layer is formed over the gate structure and the source/drain contact structure. Afterwards, the insulating layer is patterned to form a self-aligned via opening by multiple etching processes (which may be referred to as a multi-step etching process) using the capping layer as a hard mask, so that the source/drain contact structure is exposed. One of the multiple etching processes uses an etching gas mixture that includes an oxygen gas to recess the insulating layer directly above the source/drain contact structure. Afterwards, another etching process uses another etching gas mixture that includes a hydrogen gas to remove the remaining insulating layer directly above the source/drain contact structure, so that the source/drain contact structure is exposed.

The etching gas mixture including the oxygen gas can remove the polymer residue formed in the via opening during the recessing of the insulating layer to increase the etching rate, thereby reducing the process time. Moreover, the via opening profile can be improved due to the removal of the formed polymer residue, so as to maintaining the etching rate during the recessing of the insulating layer. In addition, the etching gas mixture including the hydrogen gas can prevent the source/drain contact structure from being damaged, such as corrosion or oxidation. Such etching gas mixtures provide a high etching selectivity between the insulating layer and the capping layer. As a result, the gate structure can be protected by the capping layer during the multiple etching processes. Therefore, a short circuit between the gate structure and the source/drain contact structure can be prevented even if the via opening overreaches from the position above the source/drain contact structure to the position above the gate structure.

FIGS. 1A to 1D illustrate perspective views of various stages of manufacturing a semiconductor device structure and FIGS. 2A to 2Q illustrate cross-sectional representations of various stages of manufacturing a semiconductor device structure in accordance with some embodiments. In addition, FIGS. 2A to 2D illustrate the cross-sectional representations of the semiconductor device structure shown along line 2-2′ in FIGS. 1A to 1D in accordance with some embodiments. In some embodiments, the semiconductor device structure is implemented as a fin field effect transistor (FinFET) structure.

As shown in FIGS. 1A and 2A, a substrate 100 is provided. In some embodiments, the substrate 100 is a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g. with a P-type or an N-type dopant) or undoped. In some embodiments, the SOI substrate is fabricated using a wafer bonding process, a silicon film transfer process, a separation by implantation of oxygen (SIMOX) process, another applicable method, or a combination thereof. In some embodiments, the substrate 100 is a silicon wafer. The substrate 100 may include silicon or another elementary semiconductor material such as germanium. In some other embodiments, the substrate 100 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.

Afterwards, multiple recesses (or trenches) are formed in the substrate 100 to successively form fin structures over the substrate 100, in accordance with some embodiments. As a result, multiple fin structures 102 are formed between the recesses. As shown in FIGS. 1A and 2A, one of the fin structures 102 is shown. In some embodiments, one or more photolithography and etching processes are used to form the fin structures 102 between the recesses.

Isolation features 110 are then formed in the recesses to surround lower portions of the fin structures 102, as shown in FIGS. 1A and 2A in accordance with some embodiments. The isolation features 110 are used to define and electrically isolate various device elements formed in and/or over the substrate 100. In some embodiments, the isolation features 110 include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof. The insulating layer for the formation of the isolation features 110 may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), low-K dielectric materials, and/or another suitable dielectric material and may be deposited by a flowable CVD (FCVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another applicable process.

Afterwards, dummy gate structures 111 a, 111 b, and 111 c are formed across the fin structure 102 over the substrate 100 to cover the isolation features 110, as shown in FIGS. 1A and 2A in accordance with some embodiments. Each of the dummy gate structures 111 a, 111 b, and 111 c includes a dummy gate dielectric layer 103 and a dummy gate electrode layer 105 formed over the dummy gate dielectric layer 103. The dummy gate dielectric layer 103 and the dummy gate electrode layer 105 may be made of silicon oxide and polysilicon, respectively.

Afterwards, gate spacers 113 are formed on the opposite sidewalls of the dummy gate structures 111 a, 111 b, and 111 c, as shown in FIGS. 1A and 2A in accordance with some embodiments. Each of the gate spacers 113 includes a first spacer layer 107 covering the sidewall of the corresponding gate electrode layer 105 and a second spacer layer 109 covering the sidewall of the first spacer layer 107, as shown in FIGS. 1A and 2A in accordance with some embodiments.

In some embodiments, the first spacer layer 107 and the second spacer layer 109 are made of different materials. For example, the first spacer layer 107 may be made of a low-K dielectric materials or another applicable dielectric material. The second spacer layer 109 is made of silicon nitride, silicon carbide, silicon oxynitride, or another applicable material.

After formation of the gate spacers 113, source/drain structures 112 are formed in the fin structure 104 laterally adjacent to and exposed from the dummy gate structures 111 a, 111 b, and 111 c, as shown in FIGS. 1A and 2A in accordance with some embodiments. In some embodiments, each of the source/drain structures 112 (which are referred to as source/drain regions) is formed by recessing the portions of the fin structure 102 laterally adjacent to the dummy gate structures 111 a, 111 b, and 111 c and growing semiconductor materials in the formed recesses in the fin structure 102 by epitaxial (epi) growth processes. For example, the semiconductor device structure may be an NMOS device, and the source/drain structure 120 may include Si, SiP, SiC, SiPC, or an III-V group semiconductor material (such as InP, GaAs, AlAs, InAs, InAlAs, or InGaAs), or the like. Alternatively, the semiconductor device structure may be a PMOS device, and the source/drain feature 120 may include Si, SiGe, SiGeB, or an III-V group semiconductor material (such as InSb, GaSb, or InGaSb), or the like. The source/drain structures 112 protrude above the isolation feature 110, as shown in FIG. 1A.

After the source/drain structures 112 are formed, an insulating layer 120 is formed over the fin structure 102 of the substrate 100 to cover the isolation feature 110 and the source/drain structures 112, as shown in FIGS. 1B and 2B in accordance with some embodiments. The insulating layer 120 may serve as an interlayer dielectric (ILD) layer. In some embodiments, the insulating layer 120 is a single layer made of silicon oxide, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. The insulating layer 120 is deposited using any suitable method, such as a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, flowable CVD (FCVD) process, the like, or a combination thereof.

Afterwards, the adjacent dummy gate structures 111 a, 111 b, and 111 c are removed and replaced by gate structures 119 a, 119 b, and 119 c, as shown in FIGS. 1B and 2B in accordance with some embodiments. In some embodiments, each of the gate structures 119 a, 119 b, and 119 c includes a gate dielectric layer 115, a gate electrode layer 117, and the gate spacers 113.

The gate dielectric layer 115 may be made of a high-K dielectric material. Examples of high-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon oxynitride, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof. In some embodiments, the gate electrode layer 117 is made of a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, or another applicable material.

Each of the gate structures 119 a, 119 b, and 119 c may further include a work functional metal layer (not shown) between the gate dielectric layer 115 and the gate electrode layer 117. The work function metal layer may be made of TiN, TaN, Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, or a combination thereof. Alternatively, the work function metal layer may be made of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, or a combination thereof.

Afterwards, the gate structures 119 a, 119 b, and 119 c is recessed to form recessing openings 126, as shown in FIGS. 1C and 2C in accordance with some embodiments. During the formation of the recessing openings 126, portions of the gate dielectric layers 115 and the gate spacers 113 are also etched, so that upper sidewalls of the insulating layer 120 are exposed by the recessing openings 126. In some embodiments, each of the gate electrode layers 117 in gate structures 119 a, 119 b, and 119 c is further etched after the upper sidewalls of the insulating layer 120 are exposed, so that the recessing openings 126 are extended to form a T-shaped profile, as shown in FIGS. 1C and 2C. As a result, the upper surface of each gate spacer 113 and the upper surface of each gate dielectric layer 115 are higher than the upper surface of the corresponding gate electrode layer 117.

Afterwards, each of the recessed gate electrode layers 117 is capped with a conductive layer 128, in accordance with some embodiments. The conductive layers 128 and the underlying gate electrode layer 117 form gate stacks of the gate structures 119 a, 119 b, and 119 c. In some embodiments, the upper surface of each gate spacer 113 is higher than the upper surface of each gate stack, as shown in FIGS. 1C and 2C. The conductive layers 128 protect the gate electrode layers 117 from damage or loss during subsequent processing. The conductive layers 128 may be made of a metal material, such as tungsten or fluorine-free tungsten.

After the conductive layers 128 are formed, a gate cut process is performed to remove one or more gate stacks of the gate structures 119 a, 119 b, and 119 c in accordance with some embodiments. For example, the gate stack of the gate structure 119 c may be removed by etching during the gate cut process. Afterwards, an insulating material 122 fills the space that is formed by the removal of the gate stack of the gate structure 119 c to form an insulating gate-cut structure 119 c′, as shown in FIGS. 1C and 2C in accordance with some embodiments. The insulating gate-cut structure 119 c′ includes the gate dielectric layer 115, the insulating material 122, and gate spacers 113 including the first spacer layers 107 and the second spacer layers 109.

The insulating material 122 may include silicon nitride, silicon oxynitride, or silicon carbon nitride, or the like. Alternatively, the insulating material 122 may include hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, or another applicable dielectric material.

Afterwards, insulating capping layers 132 a, 132 b, and 132 c are formed in the recessing openings 126 (not shown and as indicated in FIGS. 1C and 2C) to respectively cover the upper surfaces of the gate structures 119 a and 119 b, and the insulating gate-cut structure 119 c′, as shown in FIGS. 1D and 2D in accordance with some embodiments. In some embodiments, an insulating layer (not shown) used for formation of the insulating capping layers 132 a, 132 b, and 132 c is formed over the structure shown in FIGS. 1C and 2C and fills the recessing openings 126. For example, the insulating layer is made of a material that is different from the material of the insulating layer 120 and includes a metal oxide, such as ZrO₂, SiO₂, Ta₂O₅, Al₂O₃, or WO_(x). The insulating layer may be formed by performing a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, low-pressure CVD (LPCVD) process, an atomic layer deposition (ALD) process, or another applicable process.

Afterwards, a polishing process, such as a chemical mechanical polishing (CMP) process, is performed to remove the excess insulating layer above the insulating layer 120. As a result, the remaining insulating layer forms insulating capping layers 132 a, 132 b, and 132 c, and the upper surfaces of the insulating capping layers 132 a, 132 b, and 132 c are substantially level with the upper surface of the insulating layer 120, as shown in FIGS. 1D and 2D. The insulating capping layers 132 a and 132 b may serve as etch masks and protect the gate structures 119 a and 119 b in the subsequent manufacturing processes (e.g., etching processes).

After the insulating capping layers 132 a, 132 b, and 132 c are formed, a masking layer 135 is formed over the insulating layer 120 and the insulating capping layers 132 a, 132 b, and 132 c, as shown in FIG. 2E in accordance with some embodiments. In some embodiments, the masking layer 135 includes oxide-nitride-oxide (ONO) layers. In some other embodiments, the masking layer 135 includes a tri-layer structure including a bottom layer, a middle layer, and a top layer. In order to simplify the diagram, only a flat layer is depicted. The bottom layer may contain a material that is patternable and/or have anti-reflection properties. For example, the bottom layer may be a bottom anti-reflective coating (BARC) layer, such as a nitrogen-free anti-reflective coating (NFARC) layer. The bottom layer may be formed by a spin-on coating process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or another suitable deposition process. The middle layer formed over the bottom layer is a second layer of the tri-layer structure. The middle layer provides hard mask properties for the photolithography process. In addition, the middle layer is designed to provide etching selectivity from the bottom layer and the top layer. The middle layer may be made of silicon nitride, silicon oxynitride or silicon oxide and formed by a spin-on coating process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or another suitable deposition process. The top layer is formed over the middle layer and is a third layer of the tri-layer structure. The top layer may be positive photoresist or negative photoresist.

Afterwards, an opening 137 is formed through the masking layer 135 and the insulating layer 120 to expose the upper surfaces of some source/drain structures 112 between the gate structures 119 a and 119 b and between the gate structure 119 b and the insulating gate-cut structure 119 c′, as shown in FIG. 2F in accordance with some embodiments. In some embodiments, the opening 137 is formed by patterning the masking layer 135 and removing the insulating layer 120 using the patterned masking layer 135 as an etch mask.

During the removal of the insulating layer 120, the insulating capping layers 132 a, 132 b, and 132 c are also used as etch masks, so as to define source/drain contact regions between the gate structures. For example, the source/drain contact regions are between the gate structures 119 a and 119 b and between the gate structure 119 b and the insulating gate-cut structure 119 c′. A portion of the masking layer 135 and portions of the insulating capping layers 132 a, 132 b, and 132 c are also be removed during the etching for formation of the opening 137. However, the gate structures 119 a, 119 b, and the insulating gate-cut structure 119 c′ still can be protected by the insulating capping layers 132 a, 132 b, and 132 c.

Afterward, a conductive material 140 is formed over the patterned masking layer 135 and fills the opening 137, as shown in FIG. 2G in accordance with some embodiments. In some embodiments, the conductive material 140 is made of Co, Cu, W, Ni, Al, Mo, or the like. The conductive material 140 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition, (PVD) process, an atomic layer deposition (ALD) process, an electroless deposition (ELD) process, an electrochemical plating (ECP) process, or another applicable process.

The excess conductive material 140A is removed by a polishing process, as shown in FIG. 2H in accordance with some embodiments. In some embodiments, the polishing process, such as chemical mechanical polishing (CMP) process, is performed on the conductive material 140 until the insulating capping layers 132 a, 132 b, and 132 c are exposed and planarized. The remaining conductive material 140 forms a contact structure 142 a between and laterally adjacent to the gate structures 119 a and 119 b, and a contact structure 142 b between and laterally adjacent to the gate structure 130b and the insulating gate-cut structure 119 c′. Those contact structures 142 a and 142 b electrically connect the corresponding source/drain structures 112 and therefore they are also referred to as self-aligned source/drain contact structures or self-aligned source/drain electrodes.

Afterwards, the masking layer 135 is removed. The contact structures 142 a and 142 b are recessed to form recess openings 144 a and 144 b above the contact structures 142 a and 142 b, respectively, as shown in FIG. 2I in accordance with some embodiments. In some embodiments, after the contact structures 142 a and 142 b are recessed, the recess opening 144 a is formed between the gate structures 119 a and 119 b, and a recess 144 b is formed between the gate structure 119 b and the insulating gate-cut structure 119 c′. As a result, the upper surfaces of contact structure 142 a and the contact structure 142 b are lower than the upper surfaces of the insulating capping layer 132 a, 132 b, and 132 c. In some embodiments, the upper surfaces of the insulating capping layer 132 a, 132 b, and 132 c are substantially level with the upper surfaces of the conductive layers 128 in the gate structures 119 a and 119 b, as shown in FIG. 2I.

After the contact structures 142 a and 142 b are recessed, insulating layers 150 and 152 are successively formed over the insulating layer 120 and cover the insulating capping layers 132 a, 132 b, and 132 c, as shown in FIG. 2J in accordance with some embodiments. In some embodiments, the insulating layer 150 fills the recess openings 144 a and 144 b (not shown and as indicated in FIG. 2I) and serves as an etch stop layer for the subsequent etching of the insulating layer 152. The insulating layer 150 is made of a material that is different from the material of the insulating capping layers 132 a, 132 b, and 132 c. For example, the insulating layer 150 may be made of silicon nitride. Alternatively, the insulating layer 150 may be made of SiCN, SiOC, SiON, SiCN, or SiOCN. The insulating layer 150 may be formed by performing a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, low pressure CVD (LPCVD) process, an atomic layer deposition (ALD) process, or another applicable processes.

In some embodiments, the insulating layer 152 serves as an interlayer dielectric (ILD) layer and is made of silicon oxide, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. The insulating layer 152 may be formed by performing by any suitable deposition method, such as a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, flowable CVD (FCVD) process, physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, the like, or a combination thereof.

After the insulating layer 152 is formed, a via opening 153 that passes through the insulating layer 152 is formed, as shown in FIG. 2K in accordance with some embodiments. In some embodiments, the insulating layer 152 is patterned by an etching process using a patterned masking layer 154 as an etch mask, so as to form the via opening 153 and expose the insulating layer 150 directly above the source/drain contact structure 142 a. The patterned masking layer 154 may be made of a photoresist material and formed by a photolithography process. In some embodiments, the formed via opening 153 is also directly above a portion of the adjacent insulating capping layer (e.g., the insulating capping layer 132 b) due to the photo overlay shift during the formation of the patterned masking layer 154, as shown in FIG. 2K. In some embodiments, since a portion of the exposed surface of the insulating layer 150 is slightly etched during patterning the insulating layer 152, the formed via opening 153 has a bottom lower than a top of the portion of the insulating layer 150 without being exposed from the via opening 153.

In some embodiments, a native oxide layer 150 a is formed on the second portion of the remaining insulating layer 150 (i.e., the exposed surface of the insulating layer 150 at the bottom of the via opening 153) after the formation of via opening 153. The top of the native oxide layer 150 a may be higher or lower than the top of the portion of the insulating layer 150 without being exposed from the via opening 153.

In some embodiments, the remaining insulating layer 150 below the via opening 153 and in the recess opening 144 a (not shown and as indicated in FIG. 2I) has a first portion (i.e., a portion of the remaining insulating layer 150 below the dashed line 149) and a second portion (i.e., a portion of the remaining insulating layer 150 above the dashed line 149). The first portion is adjacent to the contact structure 142 a and the second portion extends from a top (i.e., the dashed line 149) of the first portion.

In some embodiments, the thickness T of the remaining insulating layer 150 measured from the top of the contact structure 142 a to the bottom of the native oxide layer 150 a is in a range of from about 20 nm to about 30 nm. Moreover, the first portion of the insulating layer 150 has a thickness that occupies 30%-50% of the thickness T of the remaining insulating layer 150 and the second portion of the insulating layer 150 has a thickness that occupies 50%-70% of the thickness T of the remaining insulating layer 150.

After formation of the via opening 153 and the native oxide layer 150 a, the patterned masking layer 154 is removed from the insulating layer 152 and is replaced by a patterned masking layer 158, as shown in FIG. 2L in accordance with some embodiments. In some embodiments, the patterned masking layer 158 is formed over the insulating layer 152 and fills the via opening 153. In some embodiments, the patterned masking layer 158 is made of a material that is the same as or similar to the patterned masking layer 154 and formed by a photolithography process. Afterwards, in some embodiments, one or more etching processes may be performed to etch the insulating layers 152 and 150 and the insulating capping layer 132 a, so as to form a via opening 155 therein and expose the upper surface of the gate structure 119 a (e.g., the upper surface of the conductive layer 128 in the gate structure 119 a), as shown in FIG. 2L.

After formation of the via opening 155, the via opening 153 is extended along a downward direction by multiple etching processes (which may be referred to as a multi-step etching process) to expose the contact structure 142 a, as shown in FIGS. 2M to 2O in accordance with some embodiments. As shown in FIG. 2M, the native oxide layer 150 a near the bottom of the via opening 153 and on the second portion of the insulating layer 150 is removed by an etching process 162 (which is also referred to as a first step of the multi-step etching process). Afterwards, the via opening 153 is extended in a downward direction by the removal of the second portion of the insulating layer 150 using an etching process 164 (which is also referred to as a second step of the multi-step etching process). Afterwards, the via opening 153 is further extended in a downward direction by the removal of the first portion of the insulating layer 150 using an etching process 166 (which is also referred to as a third step of the multi-step etching process). As a result, the contact structure 142 a is exposed from the extended via opening 153.

More specifically, the patterned masking layer 158 is removed from the insulating layer 152 and is replaced by a patterned masking layer 160, as shown in FIG. 2M in accordance with some embodiments. The patterned masking layer 160 is formed over the insulating layer 152, fills the via opening 155 and expose the via opening 153. In some embodiments, the patterned masking layer 160 is made of a material that is the same as or similar to the patterned masking layer 154 and formed by a photolithography process.

Afterwards, in some embodiments, the top of the insulating layer 150 exposed from the via opening 153 is cleaned to remove the native oxide layer 150 a, as shown in FIG. 2M. In some embodiments, the exposed insulating layer 150 below the via opening 153 is cleaned by the etching process 162 using the patterned masking layer 160 as an etch mask. The removal of the native oxide layer 150 a may be advantageous to facilitate the subsequent etching process or etching step for the removal of the insulating layer 150. As a result, the total etching process time can be reduced or the occurrence of etching stop can be prevented.

In some embodiments, the etching process 162 (e.g., a dry etching process) includes exposing the native oxide layer 150 a to a plasma ignited from a treatment gas. The treatment gas includes a fluorine-containing gas. The fluorine-containing gas may include CF₄, C₄F₆, C₄F₈, or the like or a combination thereof. In some embodiments, the etching process 162 is performed in a processing chamber (such as a capacitively coupled plasma (CCP) chamber) with the treatment gas being supplied into the processing chamber. In some embodiments, carrier gases, such as argon, helium, xenon, nitrogen, or the like, are employed to carry the treatment gas into the processing chamber. A flow rate of the fluorine-containing gas in the treatment gas during the etching process 162 is in a range from about 100 sccm to about 300 sccm. Moreover, the etching process 162 may be performed with a high frequency (e.g., 40 MHz) bias power in a range from about 200 W to about 400 W and with a low frequency (e.g., 13 MHz) bias power in a range from about 30 W to about 50 W. The etching process 162 may be performed for a duration in a range from about 3 seconds to about 15 seconds. The short duration may avoid the plasma ignited from the fluorine-containing gas (e.g., CF₄ gas) interacts with the insulating capping layer 142 b that is covered by a portion of the insulating layer 150. Therefore, the loss of the insulating capping layer 142 b can be prevented or mitigated.

After the removal of the native oxide layer 150 a, the exposed insulating layer 150 below the via opening 153 is recessed or partially etched to remove the second portion of the insulating layer 150 and leave the first portion of the insulating layer 150, as shown in FIG. 2N in accordance with some embodiments. In some embodiments, the second portion of the insulating layer 150 below the via opening 153 is removed by the etching process 164 (which is also referred to as a main etching process or a main etching step) using the patterned masking layer 160 as an etch mask.

In some embodiments, the etching process 164 (e.g., a dry etching process) includes exposing the second portion of the insulating layer 150 to a plasma ignited from an etching gas mixture. The etching gas mixture includes an oxygen gas and a fluorine-containing gas that is different from the fluorine-containing gas used in the etching process 162. The fluorine-containing gas may include CHF₃, CH₂F₂, or the like or a combination thereof. In some embodiments, the etching process 164 may be an in-situ etching process that is performed in the same processing chamber as that used in the etching process 162 with the etching gas mixture being supplied into the processing chamber. In some embodiments, carrier gases, such as argon, helium, xenon, nitrogen, or the like, are employed to carry the etching gas mixture into the processing chamber. A flow rate of the oxygen gas in the etching gas mixture during the etching process 164 is in a range from about 10 sccm to about 100 sccm. A flow rate of the fluorine-containing gas in the etching gas mixture during the etching process 164 is in a range from about 100 sccm to about 200 sccm. Moreover, the etching process 164 may be performed with a high frequency (e.g., 40 MHz) bias power in a range from about 200 W to about 400 W and with a low frequency (e.g., 13 MHz) bias power in a range from about 50 W to about 200 W. The etching process 164 may be performed for a duration that is longer than the duration of the etching process 162 and is in a range from about 20 seconds to about 60 seconds.

During the etching process 164, polymer residue (such as fluorocarbon (CF_(x)) or hydrofluoric carbon (HFC)) may be formed on the sidewall of the via opening 153 due to the use of the fluorine-containing gas. The formed polymer residue may reduce the etching rate of the etching process and cause the formed via opening 153 having an undesired tapered sidewall profile. However, the use of the oxygen gas in the etching process 164 can effectively remove the formed polymer residue, so as to increase the etching rate of the etching process 164 and improve the via opening (i.e., the via opening 153) profile, thereby reducing the process time for the removal of the insulating layer 150 below the via opening 153.

In addition, as shown in FIG. 2N, a portion of the insulating capping layer 132 b is exposed on the plasma during the etching process 164. Such an etching gas mixture provides a high etching selectivity between the insulating layer 150 and the insulating capping layer 132 b. As a result, the loss of the insulating capping layer 142 b can also be prevented or mitigated. Therefore, the insulating capping layer 132 b can serve as a hard mask or an etching stop layer during the etching process 164 to protect the gate structure 119 b. Therefore, a short circuit between the gate structure 119 b and the contact structure 142 a can be prevented although the via opening 153 overreaches from the position above the contact structure 142 a to the position above the gate structure 119 b.

After the insulating layer 150 is partially removed, the left insulating layer 150 below the via opening 153 is etched to remove the first portion of the insulating layer 150, as shown in FIG. 2O in accordance with some embodiments. In some embodiments, the first portion of the insulating layer 150 below the via opening 153 is removed by the etching process 166 (which is also referred to as an overetching process or an overetching step) using the patterned masking layer 160 as an etch mask, so as to expose the contact structure 142 a.

In some embodiments, the etching process 166 (e.g., a dry etching process) includes exposing the first portion of the insulating layer 150 to a plasma ignited from an etching gas mixture. Unlike the etching gas mixture used in the etching process 164, the etching gas mixture is free of oxygen and includes a hydrogen gas and a fluorine-containing gas that is the same as or similar to the fluorine-containing gas used in the etching process 164. For example, the fluorine-containing gas may include CHF₃, CH₂F₂, or the like or a combination thereof. In some embodiments, the etching process 166 may be an in-situ etching process that is performed in the same processing chamber as that used in the etching process 164 with the etching gas mixture being supplied into the processing chamber. In some embodiments, carrier gases, such as argon, helium, xenon, nitrogen, or the like, are employed to carry the etching gas mixture into the processing chamber. A flow rate of the hydrogen gas in the etching gas mixture during the etching process 166 is in a range from about 50 sccm to about 150 sccm. A flow rate of the fluorine-containing gas in the etching gas mixture during the etching process 166 is less than the fluorine-containing gas in the etching gas mixture during the etching process 164 and is in a range from about 5 sccm to about 30 sccm. Moreover, the etching process 166 may be performed with a high frequency (e.g., 40 MHz) bias power in a range from about 200 W to about 400 W and with a low frequency (e.g., 13 MHz) bias power in a range from about 50 W to about 150 W. The etching process 166 may be performed for a duration that is longer than the duration of the etching process 164 and is in a range from about 60 seconds to about 120 seconds.

Since polymer residue may also be formed on the sidewall of the via opening 153 during the etching process 166 due to the use of the fluorine-containing gas, a low flow rate of the fluorine-containing gas is used compared to the flow rate of the fluorine-containing gas used in the etching process 164, thereby mitigating the formation of polymer residue. Moreover, the reduction of the etching rate of the etching process 166 can increase the overetching process window.

In addition, the hydrogen gas is provided for defluorination in the etching process 166, so as to prevent the contact structure 142 a from being damaged, such as corrosion or oxidation.

Similarly, as shown in FIG. 2O, such an etching gas mixture also provides a high etching selectivity between the insulating layer 150 and the exposed portion of the insulating capping layer 132 b. As a result, the insulating capping layer 132 b can serve as a hard mask or an etching stop layer during the etching process 166 to protect the gate structure 119 b. Therefore, a short circuit between the gate structure 119 b and the contact structure 142 a can be prevented although the via opening 153 overreaches from the position above the contact structure 142 a to the position above the gate structure 119 b.

After the via opening 153 is extended to expose the contact structure 142 a, the patterned masking layer 160 is removed from the insulating layer 152 and the via opening 155, and a conductive material 170 is formed over the insulating layer 152 and fills the via openings 153 and 155, as shown in FIG. 2P in accordance with some embodiments. In some embodiments, the conductive material 170 is made of Co, Cu, W, Ni, Al, Mo, or the like. The conductive material 170 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition, (PVD) process, an atomic layer deposition (ALD) process, an electroless deposition (ELD) process, an electrochemical plating (ECP) process, or another applicable process.

After the conductive material 170 is formed, a polishing process is performed on the conductive material 170 until the upper surface of the insulating layer 152 is exposed, as shown in FIG. 2Q in accordance with some embodiments. In some embodiments, the polishing process includes a chemical mechanical polishing (CMP) process. After the polishing process, the remaining conductive material 170 in the via openings 153 and 155 forms conductive via structures 172 and 174 that are electrically connected to the contact structure 142 a and the gate structure 119 a, respectively. In some embodiments, the via structures 172 and 174 have upper surfaces that are substantially level with the upper surface of the insulating layer 152, as shown in FIG. 2Q.

Embodiments of methods for forming a semiconductor device structure are provided. The formation of the semiconductor device structure includes successively forming a first insulating layer and a second insulating layer over a source/drain contact structure. Afterwards, a via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. Afterwards, the exposed first insulating layer is recessed using a first etching gas mixture to leave a portion of the first insulating layer below the via opening, and then the left portion of the first insulating layer is removed using a second etching gas mixture. The first etching gas mixture includes an oxygen gas that is capable of removing the polymer residue formed in the via opening during the recessing of the first insulating layer. As a result, the etching rate of the first insulating layer during the recessing step can be increased, thereby reducing the process time. Moreover, the via opening profile can be improved due to the removal of the formed polymer residue. In addition, the second etching gas mixture includes a hydrogen gas that is capable of preventing the source/drain contact structure from being damaged, such as corrosion or oxidation.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. The semiconductor device structure also includes a first gate spacer separated the gate stack from the source/drain contact structure and extending above top surfaces of the gate stack and the source/drain contact structure. The semiconductor device structure further includes an insulating capping layer covering the top surface of the gate stack and extending on a top surface of the first gate spacer. In addition, the semiconductor device structure includes a conductive via structure partially covering a top surface of the insulating capping layer and the top surface of the source/drain contact structure. The semiconductor device structure also includes a first insulating layer surrounding the conductive via structure and partially covering the top surface of the source/drain contact structure.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a fin structure of a substrate. The semiconductor device structure also includes a gate structure and an adjacent source/drain contact structure formed in the first insulating layer. The gate structure includes a gate electrode layer capped with a conductive layer, a gate spacer structure formed on a sidewall of the gate electrode layer, and a gate dielectric layer formed between the gate electrode layer and the gate spacer structure. The gate dielectric layer and the gate spacer structure protrude from top surfaces of the conductive layer and the source/drain contact structure. The semiconductor device structure further includes an insulating capping layer covering top surfaces of the conductive layer, the gate dielectric layer, and the gate spacer structure.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a source/drain contact structure formed over a substrate. The semiconductor device structure also includes a first gate structure and a second gate structure formed on opposite sidewalls of the source/drain contact structure. Each of the first gate structure and the second gate structure are capped with an insulating capping layer and includes a gate electrode layer, a gate spacer structure formed between the gate electrode layer and the source/drain contact structure, and a gate dielectric layer formed between the gate spacer structure and the gate electrode layer. A top surface of the source/drain contact structure is higher than a top surface of the gate electrode layer and lower than a top surface of the insulating capping layer. An interface between the source/drain contact structure and the gate spacer structure is substantially aligned with a sidewall of the insulating capping layer.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and the gate structure includes a gate dielectric layer and a gate electrode layer. The semiconductor device structure includes an insulating capping layer formed over the gate electrode layer, and the insulating capping layer covers a top surface of the gate dielectric layer. The semiconductor device structure also includes a conductive via structure formed through the insulating capping layer, and a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and a gate spacer formed adjacent to the gate structure. The semiconductor device structure includes a source/drain (S/D) contact structure formed adjacent to the gate spacer, and a conductive via structure formed over the S/D contact structure. The conducive via structure is in direct contact with the gate spacer.

In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over a substrate, and a conductive layer formed on the gate structure. The semiconductor device structure includes a gate spacer formed adjacent to the gate structure, and a source/drain (S/D) contact structure formed adjacent to the gate spacer. The semiconductor device structure includes an insulating capping layer formed on the gate spacer and the gate structure, and the insulating capping layer is in direct contact with a top surface of the gate spacer and the conductive layer.

The fins described above may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device structure, comprising: a gate structure formed over a substrate, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer; an insulating capping layer formed over the gate electrode layer, wherein the insulating capping layer covers a top surface of the gate dielectric layer; and a conductive via structure formed through the insulating capping layer, wherein a portion of the conductive via structure is lower than a top surface of the gate dielectric layer.
 2. The semiconductor device structure as claimed in claim 1, wherein the gate structure further comprises a gate spacer, and the portion of the conductive via structure is lower than a top surface of the gate spacer.
 3. The semiconductor device structure as claimed in claim 1, further comprising: a source/drain (S/D) contact structure formed adjacent to the gate structure, wherein a top surface of the S/D contact structure is lower than the top surface of the gate dielectric layer.
 4. The semiconductor device structure as claimed in claim 3, further comprising: a second conductive via structure formed on the S/D contact structure, wherein the second conductive via structure has a step-shaped structure.
 5. The semiconductor device structure as claimed in claim 1, further comprising: a conductive layer formed over the gate electrode layer, wherein the conductive layer is in direct contact with the conductive via structure.
 6. The semiconductor device structure as claimed in claim 5, wherein a top surface of the conductive layer is lower than the top surface of the gate dielectric layer.
 7. The semiconductor device structure as claimed in claim 1, further comprising: a first insulating layer formed over the insulating capping layer, wherein a portion of the first insulating layer is lower than top surface of the gate dielectric layer.
 8. The semiconductor device structure as claimed in claim 7, further comprising: a second insulating layer formed over the first insulating layer, wherein the conductive via structure penetrates through the first insulating layer and the second insulating layer.
 9. The semiconductor device structure as claimed in claim 1, further comprising: a gate cut structure formed adjacent to the gate structure, wherein a top surface of the gate cut structure is higher than a top surface of the gate electrode layer.
 10. A semiconductor device structure, comprising: a gate structure formed over a substrate, a gate spacer formed adjacent to the gate structure; a source/drain (S/D) contact structure formed adjacent to the gate spacer; and a conductive via structure formed over the S/D contact structure, wherein the conducive via structure is in direct contact with the gate spacer.
 11. The semiconductor device structure as claimed in claim 10, further comprising: an insulating capping layer formed over the gate structure, wherein the conductive via structure is in direct contact with a top surface and a sidewall surface of the insulating capping layer.
 12. The semiconductor device structure as claimed in claim 11, wherein the insulating capping layer has a T-shaped structure.
 13. The semiconductor device structure as claimed in claim 11, wherein a sidewall of the gate spacer is substantially aligned to a sidewall of the insulating capping layer.
 14. The semiconductor device structure as claimed in claim 10, further comprising: a gate cut structure formed adjacent to the gate structure, wherein a top surface of the gate cut structure is higher than a top surface of a gate electrode layer of the gate structure.
 15. The semiconductor device structure as claimed in claim 10, wherein the conductive via structure has a step-shaped structure.
 16. The semiconductor device structure as claimed in claim 10, wherein a top surface of the gate spacer is higher than a top surface of the S/D contact structure.
 17. A semiconductor device structure, comprising a gate structure formed over a substrate; a conductive layer formed on the gate structure; a gate spacer formed adjacent to the gate structure; a source/drain (S/D) contact structure formed adjacent to the gate spacer; and an insulating capping layer formed on the gate spacer and the gate structure, wherein the insulating capping layer is in direct contact with a top surface of the gate spacer and the conductive layer.
 18. The semiconductor device structure as claimed in claim 17, wherein an interface between the conducive layer and the insulating capping layer is lower than the top surface of the gate spacer.
 19. The semiconductor device structure as claimed in claim 17, further comprising: an S/D contact structure formed adjacent to the gate structure; and a conductive via structure formed on the S/D contact structure, wherein a portion of the conductive via structure is in direct contact with the insulating capping layer.
 20. The semiconductor device structure as claimed in claim 17, further comprising: a first insulating layer formed over the S/D contact structure and the insulating capping layer, wherein a portion of the first insulating layer is lower than top surface of the gate spacer. 